| 摘要 |
<p>PROBLEM TO BE SOLVED: To set a delay time as a delay circuit main body accurately and also a total delay time accurately even in the case of presence of a delay attended with read/write a memory capacitor and of a group delay of input output filter circuits. SOLUTION: This circuit has n-sets of memory cells 11-1-11-n each consisting of a memory capacitor Ci and a selector switch Si and the memory cells 11-1-11-n are driven alternately by a scanning circuit 12. In this case, a clock generating circuit 14 generating a clock pulse given to the scanning circuit 12 is configured to be phase locked loop(PLL) circuit configuration and a voltage controlled oscillator 15 generates a clock pulse (n+α).FH (αis an optional natural number), the clock pulse is divided by a frequency divider 16 by a frequency division ratio of 1/(n+α) and phase-locked to a reference frequency (horizontal synchronizing frequency) FH and the delay time is set optionally based on the numberα.</p> |
