发明名称 |
Self-registered capacitor bottom plate-local interconnect scheme for DRAM |
摘要 |
A method and structure for a lower capacitor electrode for a dynamic random access integrated circuit. A polysilicon gate layer is formed over a thin layer of oxide in a first region of a semiconductor substrate. Another oxide layer is then formed overlying the polysilicon gate layer. A polysilicon layer which was doped by S/D implant including the lower capacitor electrode self-aligns and forms overlying a second region of the semiconductor substrate and over the oxide layer on the polysilicon gate layer. A nitride layer forms on the lower capacitor electrode portion overlying the second region. Exposed portions of the polysilicon layer are then oxidized. The S/D was formed by driving dopant from implanted second layer polysilicon. Portions of polysilicon under the nitride layer corresponding to the lower capacitor electrode oxidizes at a slower rate than the exposed portions of the polysilicon. Such sequence of steps forms a self-aligned lower capacitor electrode for a dynamic random access memory integrated circuit.
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申请公布号 |
US5679595(A) |
申请公布日期 |
1997.10.21 |
申请号 |
US19960685757 |
申请日期 |
1996.07.24 |
申请人 |
MOSEL VITELIC, INC. |
发明人 |
CHEN, MIN-LIANG;TSAI, NAN-HSIUNG |
分类号 |
H01L27/04;H01L21/02;H01L21/822;H01L21/8242;H01L27/108;(IPC1-7):H01L21/70;H01L27/00 |
主分类号 |
H01L27/04 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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