Asic bus interface having a master state machine and a plurality of synchronizing state machines for controlling subsystems operating at different clock frequencies

摘要

A bus interface device for an application specific integrated circuit handles more than two different clock frequencies and allow for real time switching between the clock frequencies by subsystems of the application specific integrated circuit. In a preferred embodiment, a master state machine is provided that includes a plurality of control input lines and a plurality of control output lines, and a plurality of synchronizing state machines each coupled to one of the control output lines of the master state machine and to a separate clock frequency line. The master state machine, based on signals applied to the control input lines, selectively enables the synchronizing state machines to supply the different clock frequencies to the subsystems of the application specific integrated circuit.