| 摘要 |
A semiconductor storage apparatus includes a memory cell array containing a plurality of memory cells arranged in an array in both directions along a row and a column on a surface of a semiconductor substrate and a plurality of digit line pairs and word lines connected to the memory cell array, sense amplifiers for amplifying potential differences between the lines of the digit line pairs, Y decoders for selecting a predetermined one of the digit line pairs, load circuits for determining the potential of the digit line pairs in response to currents flowing through the digit line pairs, balancer circuits for balancing potential levels of the digit line pairs, and precharge circuits for precharging the potentials of the digit line pairs. The semiconductor storage apparatus is constructed such that the load circuits, the balancer circuits and the precharge circuits connected to the digit line pairs are located at positions of central portions of the digit line pairs so as to divide the memory cells connected commonly to the digit line pairs such that the numbers of the memory cells may be divided substantially equally into two.
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