| 摘要 |
A data processor is disclosed which shows an improved real time performance by carrying out the starting and clearing operations of a timer in response to an external trigger input. In the timer unit of the unit of the data processor, a flip-flop is set during the low level period of a count enable signal, and a prescaler and a timer are cleared and inactivated by bringing the outputs of OR gates to the-high level. As the count-enable signal goes to the high level, an edge-detection circuit output a detection pulse by detecting a level change of the external trigger signal. The flip-flop is reset by the detection pulse, and the operation of the prescaler is started and a count clock is supplied to the timer to start the counting operation of the timer.
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