| 摘要 |
Data transfer assembly comprising a primary (1) and a secondary (2) bus for electronic, digital data signals adapted to a predetermined standard, e.g. a PCI local bus, at least two electronic memory devices (3) of any known type, and means for storing and down-loading of the electronic data to and from said busses (1, 2), which also comprises at least two control devices (4, 5), e.g. a i9603RP processor from Intel3, adapted to said standard, each said control device having three ports of which: the first port is connected to one of the said memory devices (3) for loading and unloading of data to and from said memory device; the second and third ports (4P, 4S, 5P, 5S) are connected to said primary and secondary busses (1, 2) and are capable of communication with said primary and secondary busses using said standard; each control device (4, 5) being capable of loading data received from the busses, and transmitting downloaded data to the said busses (4, 5); the said control devices comprise a communication bridge, e.g. a PCI to PCI bridge, between its ports (4P, 4S, 5P, 5S), providing data communication between the primary and secondary busses. |
