Unit cell of DRAM without capacitor

摘要

The cell includes two FETs (14,15). One FET (14) has a gate electrode as well as source and drain electrodes. The second FET (15) has source and drain electrodes, and uses the drain electrode of the first FET as its gate electrode. Preferably the gate electrode of the first FET is coupled to a word line (12), while its source electrode is linked to a bit line (11). The drain electrode of the second FET is joined to a reference voltage feed line for HV application during read-out. The source electrodes of both FETs may be together coupled to a bit line. Typically the word line is coupled to gate electrode of the first FET and the drain electrode of the second FET.