| 摘要 |
A plurality of gate electrodes are formed over a semiconductor substrate. An etching stopper layer is formed on these plurality of gate electrodes. Sidewall layers are formed on the side faces of the plurality of gate electrodes. An interlayer insulating film covering the plurality of gate electrodes and the sidewall layers is formed. A contact hole is formed in the interlayer insulating film among the plurality of gate electrodes. Here, the contact hole is formed in the interlayer insulating film by making the etching rate of the etching stopper film lower than the etching rate of the interlayer insulating film and the etching rate of the sidewall layer substantially equivalent to or higher than the etching rate of the interlayer insulating film. |
