发明名称 HANDOTAIKIOKUSOCHI
摘要 Disclosed is the serial access memory having the improved precharging system of reading bit lines (4). In this serial access memory, an address pointer (9, 114) outputs a signal for selecting one of the reading bit lines (4). Meanwhile, each reading bit line (4) is provided with an MOS transistor (7) for precharging the same. By using the output of the address pointer (9, 114) to control on/off of the MOS transistor (7), the period when each reading bit line (4) is precharged is limited within the period when the reading bit line is selected. As a result, current flowing through the reading bit lines (4) during the data reading can be reduced to achieve the reduction in power consumption of the serial access memory and the increase in the operation speed.
申请公布号 JP2662822(B2) 申请公布日期 1997.10.15
申请号 JP19900070837 申请日期 1990.03.20
申请人 MITSUBISHI DENKI KK 发明人 OKIDAKA TAKENORI;MAEDA YASUNORI;MYAZAKI YUKIO
分类号 G11C11/405;G11C7/12;G11C11/401;G11C11/409;H01L21/8242;H01L27/108 主分类号 G11C11/405
代理机构 代理人
主权项
地址