发明名称 |
SUKYUUHOSEISARETAMASUTAA*KUROTSUKUSHINGOHATSUSEISOCHI |
摘要 |
<p>A digital TV receiver includes an apparatus for generating a skew corrected clock. The apparatus consists of a fixed frequency, free running oscillator (22) for producing a signal (FFOS) having a frequency which is a fixed integer multiple K of the desired nominal frequency of the skew-corrected clock signal, and a divide-by-K circuit (30) which is reset once every horizontal line. The divide-by-K circuit comprises a divide-by-m circuit connected in series with a flip-flop (50), with said divide-by-m circuit (40) being reset by a first control signal (FCS) once every horizontal line. The apparatus additionally includes means (Fig. 2/SCS) for preventing the output of the flip-flop (50) from changing while the divide-by-m circuit is reset in response to the first control signal (FCS).</p> |
申请公布号 |
JP2663351(B2) |
申请公布日期 |
1997.10.15 |
申请号 |
JP19880076678 |
申请日期 |
1988.03.31 |
申请人 |
AARU SHII EE TOMUSON RAISENSHINGU CORP |
发明人 |
ERITSUKU DAGURASU ROOMUZUBAAGU;RATSUSERU TOOMASU FURINGU |
分类号 |
H04N5/04;H04N5/12;H04N7/26;H04N9/44;H04N9/45;H04N9/64;H04N9/896;H04N11/04;(IPC1-7):H04N11/04 |
主分类号 |
H04N5/04 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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