Semiconductor memory having redundancy memory decoder circuit

摘要

A redundancy decoder circuit includes an output line U which takes an active level when an access address supplied thereto is coincident with a redundant address programmed therein. This circuit further includes a fuse F which is blown to deactivate the decoder or not blown to activate the decoder, a latch circuit latching a level responsive to a blown or not-blown state of the fuse, and a transistor controlled by the latch circuit to forcibly hold the output line at an inactive level when the fuse is blown.