| 摘要 |
The invention provides a technique for forming a MOS transistor with reduced leakage current and a shorter channel length between source and drain electrodes. The transistor includes a gate electrode between raised source and drain electrodes that are formed from epitaxial silicon. Typically, the raised source and drain electrodes are thin where the intersect the gate electrode so that epitaxial notches are formed between the gate sidewall insulation and the source/drain electrodes. To protect the source/drain junction areas underlying the epitaxial notches from undesired penetration of doping impurities used in the fabrication of the electrodes, the notches are covered with insulation material. In a special process step, performed between forming the epitaxial layers and implanting the layers with dopants to form source and drain electrodes, insulation material is added to the initial, relatively thin, gate sidewalls that insulate the gate electrode from the source/drain electrodes. Any subsequent diffusion of doping impurities into the underlying source/drain junction areas occurs at a uniform rate so that the junction depth beneath the notches is not deeper than other regions of the junction areas. Thin uniform junction areas permit the channel length between source/drain electrodes to be shortened so that transistors may be packed more densely on a substrate. A raised source/drain MOS transistor with gate insulation sidewalls to fill epitaxial notches is also provided.
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