| 摘要 |
A clock recovery circuit including a digital locked loop is disclosed. The digital locked loop provides a wide numerically controlled bandwidth for recovering a heavily gapped received clock signal with large variations in frequency. The disclosed embodiments are directed to a digital locked loop for providing a recovered clock signal for controlling the rate at which a parallel to serial converter receives data from the first-in first-out buffer. The digital locked loop uses the state of the first-in first-out buffer as more or less than half full as a phase comparison between the recovered clock signal and the received clock signal. |
