FLASH MEMORY ADDRESS DECODER WITH NOVEL LATCH STRUCTURE

摘要

A flash memory address decoder with a novel latch structure includes an address terminal to receive an address signal, a procedure terminal to receive a procedure signal, a power terminal to receive a power signal and a flash transistor array having a plurality of wordlines, sourcelines and bitlines. A sourceline decoder is coupled to the address terminal and the power terminals and configured to decode a portion of the address and provide an operational voltage on at least one of the sourcelines. A wordline decoder is coupled to the address terminal and the power terminal and includes a plurality of latches coupled to the wordlines. The wordline decoder is configured to decode a portion of the address and to latch selected wordlines to simultaneously provide a plurality of operational voltages on different ones of the wordlines. A bitline decoder is coupled to the address terminal and configured to decode a portion of the address and to select a plurality of the bitlines as selected bitlines. A sense amplifier is coupled to the bitline decoder and configured to sense current on the selected bitlines and to generate a data word corresponding to the current. A memory controller is coupled to the procedure terminal, the power terminal, the sourceline decoder, the wordline decoder, the bitline decoder and the sense amplifier, and is configured to control the sourceline decoder, the wordline decoder, the bitline decoder and the sense amplifier to perform a procedure responsive to the procedure signal.