Hierarchical word line structure for semiconductor memory device

摘要

The hierarchical word line structure includes a number of memory array blocks each including a row decoder, and a number of main word lines connected to the row decoder and each arranged in one of a number of rows. A number of sub-word drivers each have an input node, a power node and an output node and are arranged in a number of columns and sub-rows between two neighbouring ones of the main word lines. The input node of each sub-word driver in a row is connected with its associated main word line. Codings lines connected to the power nodes of the sub-word line drivers are arranged in the same column. The word line structure includes the sub-word drivers of two neighbouring columns with their respective output nodes being opposed to one another, and a sub-word line extends from the sub-word driver in each sub-row toward the neighbouring column. A corresponding metallic word strap line is connected at its one end to the output node of the associated sub-word driver and at its other end to an intermediate point of the sub-word line. The sub-word line may be connected to the sub-word driver only via the word strap line, or the sub-word line may be segmented into a first segment connected to the output node of the sub-word driver and a second segment connected to the other end of the word strap line. Or, the line is connected at one end of it to the output node of the corresponding sub-word driver in common with the one end of the word strap line.