发明名称 D*AHENKANKI
摘要 <p>PURPOSE:To also cause an output waveform to be a low glitch by making the digital data of a same phase and a reverse phase at first to data from a pallet RAM, after that, once holding the data to a latch circuit and arranging the phase from the reading of the data. CONSTITUTION:The value of an Iconst 20 to be supplied from a constant current source is set from an external part so that a gate voltage V101 and a drain voltage V102 of a transistor Q21 can be equal (V101=V102). Accordingly, the current of an output CUT30 in a current source circuit is determined by the switching of the two kinds of the data, which are the input signals of transistors Q31 and Q41 and in mutually complementary relation. The switching levels of the transistors Q31 and Q41 are set to the cross point of rising and falling voltage waveforms for the two kinds of the data of the same phase and reverse phase. Thus, the timing of turning-on and off can be matched for the transistors Q31 and Q41 and the condition of the turning on and off can be made extremely short. Then, the switching can be executed with avoiding the condition of the turning-on and off and the output signal can be caused to be the low glitch.</p>
申请公布号 JP2661126(B2) 申请公布日期 1997.10.08
申请号 JP19880096216 申请日期 1988.04.19
申请人 SEIKOO EPUSON KK 发明人 NAKADA AKIRA;KASAHARA SHOICHIRO
分类号 G06F3/153;G06F1/06;H03M1/66;H04N5/14;H04N9/44;H04N9/64;H04N11/04;(IPC1-7):H04N11/04 主分类号 G06F3/153
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