| 摘要 |
PURPOSE:To provide a logic circuit which can perform a series of phase differ ence detecting and phase confirming operations at a high speed. CONSTITUTION:A logic circuit 100 which confirms the phase differences of plural signals by a clock synchronizing expression is provided with the 1st and 2nd phase difference absorbing memories 1a and 1b which store the position signals FP1 and FP2 showing the signal head positions respectively, the 1st and 2nd writing state control circuits 5a and 5b which inhibit the write of the subsequent position signals into both memories 1a and 1b when the signals FP1 and FP2 are written into the memories 1a and 1b respectively, and the 1st end 2nd phase difference deciding circuits 3a and 3b which fetch the signal FP1 and FP2 stored in both memories 1a and 1b to decide the phase difference of both signals FP1 and FP2 and then produces the output signals after confirming the coincidence or discordance of both signals FP1 and FP2. In such a constitution, a series of phase difference detecting anti phase confirming operations can be carried out at a high speed. |
