| 摘要 |
Disclosed is a word line drive circuit of an LSI semiconductor memory device comprising a plurality of word lines, a plurality of memory cells connected each to the word line, a row decoder and drive circuit connected to said plurality of word lines for selecting and driving the word line from a first voltage level to a second voltage level in response to an input address signal in a memory cycle, and a negative voltage generating circuit connected to the plurality of word lines for generating a negative voltage in a non-memory cycle, wherein the word line drive circuit comprises a reset circuit for maintaining the selected word line at an intermediate voltage level between the first voltage level and the second voltage level at least in one point of an end point and an starting point of the memory cycle. |
