发明名称 |
Method and apparatus for parallel testing of memory circuits |
摘要 |
A memory circuit 14 is provided having a data register (20) coupled to the output of the memory cell array (16). The output of the data register (20) may be selectively output, allowing a plurality of memory circuits (14) to be tested in parallel with a substantial increase in efficiency. Furthermore, test data can be written to the memory cell arrays (14) while previous test data is read from the memory circuits for optimum efficiency.
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申请公布号 |
US5675544(A) |
申请公布日期 |
1997.10.07 |
申请号 |
US19920873523 |
申请日期 |
1992.04.21 |
申请人 |
TEXAS INSTRUMENTS INCORPORATED |
发明人 |
HASHIMOTO, MASASHI |
分类号 |
G11C29/26;G11C29/56;(IPC1-7):G11C29/00 |
主分类号 |
G11C29/26 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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