发明名称 |
High performance multi-mesa field effect transistor |
摘要 |
A high performance transistor includes mesa structures in a conduction region, favoring corner conduction, together with lightly doped mesa structures and mid-gap gate material also favoring operation in a fully depleted mode. Mesa structures are formed at sub-lithographic size and pitch as recesses or by epitaxial growth together with exposure of a resist by an interference pattern generation with illuminating radiation and multiple exposures using a mask shifted by a sub-lithographic distance. For an NFET, conduction electron and hole distribution profiles in the mesa structures and gate capacitance are adjusted with dielectric thickness, including deposition of oxide from a liquid solution at room temperature. Transconductance may be altered by change of the aspect ratio of the mesa structures. Lightly doped drain structures are also formed at sub-lithographic sizes by self-aligned processes.
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申请公布号 |
US5675164(A) |
申请公布日期 |
1997.10.07 |
申请号 |
US19950486221 |
申请日期 |
1995.06.07 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
BRUNNER, TIMOTHY A.;HSU, LOUIS L.;MANDELMAN, JACK A.;WANG, LI-KONG |
分类号 |
G03F7/20;H01L21/027;H01L21/28;H01L21/308;H01L21/336;H01L29/423;H01L29/51;H01L29/78;(IPC1-7):H01L29/78 |
主分类号 |
G03F7/20 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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