发明名称 |
Verfahren und Anordnung zum Verbinden integrierter Schaltungen in drei Dimensionen |
摘要 |
<p>The subject of the present invention is a method and a device for interconnecting stacked semiconductor wafers, each wafer containing an integrated circuit. To this end, the semiconductor wafers (P) are stacked and rendered rigid with one another. In one embodiment, their connection pins are each connected with the aid of a wire (F) to any one of the faces of the stack save one (B), intended to be in contact with a printed circuit. The connection of the wafers to one another and of the latter with the integrated circuit, is carried out on the faces (FV, FS, FL) of the stack. <IMAGE></p> |
申请公布号 |
DE69126599(T2) |
申请公布日期 |
1997.10.02 |
申请号 |
DE1991626599T |
申请日期 |
1991.12.06 |
申请人 |
THOMSON-CSF, PARIS, FR |
发明人 |
LEROY, MICHEL, F-92045 PARIS LA DEFENSE, FR;VAL, CHRISTIAN, F-92045 PARIS LA DEFENSE, FR |
分类号 |
H01L23/52;H01L21/60;H01L25/065;H01L27/00;(IPC1-7):H01L25/065 |
主分类号 |
H01L23/52 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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