| 摘要 |
<p>In a memory device that comprises an internal bus for the transfer of data and reporting signals from and to the memory and output pre-buffers (1L, 1H) for the transfer of data to output terminals (2L, 2H) of said memory, a pulse generation circuit for the synchronized loading of data in an output pre-buffer, which has the particularity that it comprises: synchronization generation means (7); means (5) for reproducing the propagation delays of the data transmitted to the output terminals (2L, 2H); and means (6) for reproducing the propagation delays of the output pre-buffers (1L, 1H); the synchronization means (7) are adapted to synchronize the generation of at least one pulse that is synchronized with the propagation delays reproduced by the data propagation delay reproduction means (5), and the pulse is adapted to enable the loading of the data in the output pre-buffers (1L, 1H); the synchronization is provided as a consequence of the assured presence of the data, and the synchronous pulse is restored after a time that is equal to the delay introduced by the means (6) for reproducing the propagation delays of the output pre-buffers, so as to update the configuration of the output pre-buffers (1L, 1H) in the time interval determined by the synchronous pulse. <IMAGE></p> |
