| 摘要 |
<p>A data reading path management architecture for a memory device, particularly of the non-volatile type, comprising a memory matrix and data sensing means (2) that are adapted to receive in input the data of the memory matrix for reading, which has the particularity that the memory matrix is divided into at least two half-matrices (1L, 1R); each one of the two half-matrices has a reference line (ROW-RIF) that is adapted to constitute a reference for reading the other half-matrix; the data sensing means (2) receive in input the data from one half-matrix (1L, 1R) and the reference from the other half-matrix (1L, 1R); the data sensing means (2) are adapted to transmit, according to a control timing, the data on an internal bus (DATA-BUS) for their transmission in output. <IMAGE></p> |
