Method and circuit for controlling digital processing phase-locked loop for network synchronization

摘要

The present invention discloses a control algorithm of digital processing-phase locked loop(DP-PLL) for network synchronization to prevent phase-hit generated at the time of transition of the operation mode. The control process of DP-PLL includes the steps of setting a value corresponding to an initial center frequency at a voltage-controlled oscillator at the initial stage and bringing into a free-run mode determining the mode to be in a normal state unless the abnormality of the reference clock signal is not monitored at the free-run mode and transferring the free-run mode into the fast mode storing phase deviation data for a predetermined period of time at the initial process and computing its average value to set the average value as a reference phase deviation of the fast mode computing and controlling a control value of the voltage controlled oscillator to converge the phase deviation data into the reference phase deviation and transferring the fast mode into a normal mode once the fast mode becomes stable, storing the phase deviation data for a predetermined period of time at the initial process, measuring an average value to set the average value as a reference phase deviation of the normal mode, and computing and controlling a control value of the voltage-controlled oscillator that is converged into the reference phase deviation.