| 摘要 |
Among a plurality of flip-flops coupled with a combinational logic and supplied with a plurality of different clocks, a number of flip-flops are selected so that a respective one of the selected flip-flops is supplied with an associated one of the clocks and has an output thereof connected to one or more of the selected flip-flops, of which at least one is supplied with one of the clocks different from the associated clock of the respective one of the selected flip-flops, and are designed as scan flip-flops to be serially connected to constitute a partial scan path circuit. |
