发明名称 HANDOTAIKIOKUSOCHIOYOBISONOSEIZOHOHO
摘要 PURPOSE:To reduce a soft error ratio by forming a pillar of a projection on an insulation layer which is buried in a substrate. CONSTITUTION:A groove 6 is formed lengthwise and breadthwise using a junction wafer as a starting material and the oxide film 2 as an etching stopper by anisotropy etching from a substrate 18 to form a plurality of pillar-like projections 51, 52... of semiconductor which are isolated by the groove 6. A MOS capacitor is formed at a lower section of the pillar-like projection 5, and a MOSFET at an upper section. In this way, soft error is reduced and it becomes possible to form a DRAM which enables high integration and a large capacity.
申请公布号 JP2659991(B2) 申请公布日期 1997.09.30
申请号 JP19880075610 申请日期 1988.03.29
申请人 TOSHIBA KK 发明人 HIEDA KATSUHIKO
分类号 H01L27/10;H01L21/336;H01L21/8242;H01L27/108;H01L29/423;H01L29/78 主分类号 H01L27/10
代理机构 代理人
主权项
地址