| 摘要 |
PURPOSE:To reduce the increase of a hardware in the case the detection of coincidence is desired among plural addresses by storing a debugging object instruction address into a branching history table. CONSTITUTION:A debugging information memory 4 is set at '0' at normal branching estimation and therefore a predictive branching destination detecting flag 7 is set at '1' with a pseudo fault flag 9 set at '0' respectively. Then a predictive branching destination address is detected. Since the memory 4 is set at '1' with a debugging object address, a signal line 115 is set at '0' and the flag 7 is not turned on when the coincidence is obtained between an instruction address register 1 and a branching address memory 2. When a debugging frequency memory 5 is set at '0', the output 115 of a zero checking circuit 12 is set at '1' and the flag 9 is turned on. Thus plural debugging addresses can be set with the reduced increase of the hardware quantity. |
