发明名称 NETSUTOWAAKUNOJIKOKUJOHODOKIHOSHIKI
摘要 PURPOSE: To synchronize devices with a high quality with respect to time by correcting an incorporated clock by the extent or average deviation, which is calculated from time difference information based on time information of a prescribed number of operations, and the average delay time from a master device. CONSTITUTION: In an information processor 10, an average data transmission delay time Tp of a communication network is calculated by an average delay time calculation means 24 in accordance with elapsed time information of a prescribed number of operations recorded in an elapsed time calculating and recording means 23. In an information processor, an extent Td of average time information deviation between devices 10 and 30 is calculated by an average deviation extent calculation means 44 in accordance with time difference information of the prescribed number of operations recorded in a time difference calculating and recording means 43. The processor 10 sets the time Tp to a delay time report signal Tps of the format to send it to the processor. It is received by a time correction means 45, and the time Tp is taken out and is subtracted from the extent Td or deviation to correct the time of an internal clock 41. Thus, the clock of the processor 30 is synchronized with an internal clock 21 of the processor 10.
申请公布号 JP2658962(B2) 申请公布日期 1997.09.30
申请号 JP19950084749 申请日期 1995.03.15
申请人 NIPPON DENKI KK 发明人 SATO SHINICHI
分类号 G04G7/00;G06F1/14;G08C15/06;H04L7/00;H04L12/28;H04Q9/04 主分类号 G04G7/00
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