发明名称 |
Snooping of I/O bus and invalidation of processor cache for memory data transfers between one I/O device and cacheable memory in another I/O device |
摘要 |
In a computer system that contains an input output (I/O) bus connecting to I/O devices, a central processing unit (CPU), a CPU cache memory, a system memory not directly accessible via the I/O bus, and a system bus used for conducting data transfers between the I/O bus and both the CPU cache and system memory, a method and apparatus are provided to allow addressable memory locations in both the system memory and I/O devices coupled to the I/O bus to be cacheable in the CPU cache. The I/O bus supports data transfers between pairs of I/O devices, as well as data transfers between individual I/O devices and the system which presents a problem of maintaining coherency in the CPU cache when data is written by one I/O device to a cacheable memory location in another I/O device. The present solution employs a snoop/data invalidation function at the system interface to the I/O bus to determine when a memory location in an I/O device coupled to the I/O bus is being written to by another I/O device coupled to the I/O bus. If such a write is taking place, it is then determined if the address of the location being written is in an address range predesignated as cacheable; if so, then the CPU cache controller or other device controlling the CPU cache is notified that memory at a cacheable location in an I/O device has been overwritten.
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申请公布号 |
US5673414(A) |
申请公布日期 |
1997.09.30 |
申请号 |
US19940327136 |
申请日期 |
1994.10.21 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
AMINI, NADER;BOURY, BECHARA FOUAD;BRANNON, SHERWOOD;HORNE, RICHARD LOUIS |
分类号 |
G06F12/08;(IPC1-7):G06F13/00;G06F13/36;G06F13/40 |
主分类号 |
G06F12/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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