| 摘要 |
In a photolithographic step in the fabrication of semiconductor integrated circuits, alignment of the photomask pattern with two patterns defined on the wafer in two previous steps is checked simultaneously. Each of the two patterns on the wafer is provided with an alignment check pattern consisting of a plurality of rectangular pattern elements arranged parallel to each other in a row at a first constant pitch. The pattern elements of one check pattern are respectively opposite to the pattern elements of the other check pattern. On the photomask there is an alignment check pattern consisting of a plurality of rectangular and relatively long pattern elements arranged parallel to each other in a row at a second constant pitch. In the composite layout of the three alignment check patterns, each pattern element of the check pattern on the photomask partly ovelaps a pattern element of each of the two check patterns on the wafer. Alignment accuracy is checked by examining which pattern element of the check pattern on the photomask is in accurate alignment with a pattern element of each check pattern on the wafer. Alignment of the photomask pattern with more than two patterns on the wafer can be checked in the same manner.
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