发明名称 KYARIAKANCHENSACHOSEIKI
摘要 PURPOSE:To simplify the adjustment and to prevent mis-adjustment by automating the delay adjustment between carriers implemented at system built-up or the like. CONSTITUTION:An absolute delay detection circuit 11 receives data signal strings D1-Dn demodulated from a signal sent via a standby line with n-sets of carriers and frame synchronization pulses F1-Fn to be recovered respectively and detects a data signal string latest and sends information Sa. A relative delay detection circuit 12 receives a data signal string, a frame synchronization pulse and the information Sa and detects a relative delay difference of the n-sets of data signal strings based on a data signal string latest to generate delay control data S1-Sn. A delay data storage circuit 13 stores the delay control data and sends it, Delay circuits 1-n give each data signal string and a frame synchronization pulse in response to the delay control data S1-Sn to make the delay difference between the n-sets of data signal strings coincident with each other.
申请公布号 JP2658658(B2) 申请公布日期 1997.09.30
申请号 JP19910223787 申请日期 1991.09.04
申请人 NIPPON DENKI KK 发明人 MUTO HIDEYUKI
分类号 H04L1/22;H04L7/00;H04L7/08 主分类号 H04L1/22
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