发明名称 |
PHASE LOCKED LOOP WITH CONTROLLABLE RESPONSE TIME. |
摘要 |
An arrangement for selectively controlling the response time of a type II phase locked loop (PLL), especially one which includes a phase detector and an amplifier of a feedback type of integrator within an IC, comprises a controllable filter stage coupled in cascade with the amplifier. The controllable filter stage includes a filter section and a switching arrangement for selectively bypassing the filter section in response to a mode determining control signal. In the described embodiment, the PLL controls the frequency of a local oscillator of a tuner and the second filter section has an amplitude versus frequency response for increasing the response time of the PLL during a fine tuning mode so that a demodulator can continue to operate properly during the fine tuning mode.
|
申请公布号 |
MX9606747(A) |
申请公布日期 |
1997.09.30 |
申请号 |
MX19960006747 |
申请日期 |
1996.12.19 |
申请人 |
THOMSON CONSUMER ELECTRONICS, INC. |
发明人 |
DAVID MARK BADGER |
分类号 |
H03L7/093;H03J1/00;H03J5/02;H03L7/107;H04L27/00;H04L27/233;(IPC1-7):H03J07/00 |
主分类号 |
H03L7/093 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|