Differential delay line circuit for outputting signal with equal pulse widths

摘要

A signal delay device is provided which enhances noise immunity by using a differential circuit, but also maintains the phase of the input clock signals. This device will also correct the phase of clock signals which are input to the delay device in an out of phase condition. The present invention is a delay circuit that includes functionally connecting each of the output signals with each of the input signals. Thus, the output signals are dependent on the same input and the steady state condition is the point where the leading edge of a first output signal intersects the trailing edge of a second output signal at the point which corresponds to one half of the pulse height of both signals. Since the signals are complements of one another, they will cross at 50% of their pulse height when they are "in phase". Thus, the present invention will maintain "in phase" input signals and seek an "in phase" condition for signals that are input to the delay circuit which are "out of phase".