Semiconductor memory device in which leakage current from defective memory cell can be suppressed during standby

摘要

A bit line precharge potential supply interconnection and a bit line pair are connected via N channel MOS transistors in which the gate potentials are controlled by an equalizing signal and a P channel MOS transistor which is in connection with the connection point of N channel MOS transistors. The P channel MOS transistor has its gate connected to a column selecting line. When there is a failure due to short-circuit between a bit line and a word line, the column selecting line is set such that it would be at "H" level during the standby period by disconnecting a fuse element. Accordingly, the connection between the bit line pair and the precharge potential supply interconnection is cut off during the standby period, preventing generation of leakage current and thus suppressing increase in power consumption.