| 摘要 |
PURPOSE:To reduce an area of a memory cell by a method wherein a groove-type capacitance element and a diffusion layer adjacent to it are used as gate electrodes and a semiconductor thin-film transistor which can become a channel region is formed along the upper-part side wall of the groove-type capacitance element. CONSTITUTION:A device isolation region 3 is formed on p<+>/p epitaxial substrates 1, 2 such as, e.g., Si substrates; an n-type diffusion layer 12 is formed in the whole device region. Then, a vertical groove 4 which leaves the n-type diffusion layer 12 on both sides is formed; a thin insulating film 6 is formed on the inner surface of the groove 4 and on the surface of the diffusion layer 12. A conductive substance is filled into the groove 4; a semiconductor thin film is deposited on the whole face of the substrate. Then, an impurity is implanted into the whole face in the direction perpendicular to the substrate; a source region and a drain region 8a, 8b are formed on the surface of the diffusion layer 12 and on the upper part of the conductive substance 7 inside the groove 4; a channel region 8c is formed on the side wall at the upper part inside the groove 4. After that, the thin-film layers 8a, 8b, 8c are patterned; an interlayer film 9 is deposited; a contact 10 is formed on the device isolation region 3; a metal wiring layer 11 is deposited on the interlayer film 9 and is patterned. |
