| 摘要 |
<p>The circuit comprises a logic gate circuit (1) such as NOR, NAND, etc., and an inverter circuit (2). A reset signal (PON) is obtained at an output of the logic gate circuit (1), which is also connected to an input of the inverter circuit (2). An output of the inverter is connected to one of two inputs of the logic gate circuit. An internal signal ( phi 1) generated in an internal circuit in accordance with an external signal generated in an external circuit after the finish of a power-on is supplied to the remaining input of the logic gate circuit (1) to change the output state thereof. Consequently, the generation of a reset signal becomes precise, and a power consumption is reduced. <IMAGE></p> |
