Central processor control unit (CPU) arrangement for cyclically repeated processes in IC engine

摘要

The arrangement includes a calculation unit (10) serving ads the central control unit (CPU) for the calculation of control signals in response to detected operating parameters (n, T, p ...), and at least one output unit (K1... Kn) for the output of the control signals. An output unit comprises a first and a second register (20, 21), which are both respectively connected with the calculation unit, a comparator (26) whose first input is supplied with a clock signal in proportion to an angle, and a counter (25) whose clock input is supplied with a signal sequence with a fixed clock frequency. The first register (20) is connected with the second input of the comparator, and the second register (21) is connected with the counter. The output unit contains a control arrangement (27) which is supplied with the output signal of the comparator, and which stands in reciprocal connection with the output of the counter. An output of the control arrangement is connected with an output switch stage.