Reduced footprint semiconductor processing system

摘要

The invention relates to a wafer processing system (10) having processing chambers on at least two levels (16, 22) wherein the levels are vertically displaced relative to each other. Preferably, at least one chamber on the second level (22) is located above a chamber on the lower level (16) in a substantially overlapping relationship. An elevator chamber (24, 26) is provided to transport work pieces between the two processing levels. In this manner, the floorspace footprint of the processing system (10) can be reduced. <IMAGE>