发明名称 Integrated circuit incorporating a test circuit
摘要 Disposed in an integrated circuit is a test circuit having: a plurality of tristate buffers each for supplying, in a test mode, a charging current to a stray capacitance of a corresponding wire on a printed circuit board through a corresponding signal terminal of the integrated circuit; and a plurality of exclusive-OR gates each for supplying a logical signal having a pulse width indicative of a time interval between an input transition time and an output transition time of a corresponding tristate buffer. A difference in capacitance between a state where a signal terminal is being properly electrically connected to a wire on the printed circuit board and a state where the signal terminal is being improperly electrically connected thereto, is converted into a difference in pulse width of a logical signal, based on which a defective soldering of open failure in the signal terminal is detected.
申请公布号 US5671233(A) 申请公布日期 1997.09.23
申请号 US19960646564 申请日期 1996.05.08
申请人 MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. 发明人 KAMADA, TAKEHIRO
分类号 G01R31/3185;(IPC1-7):G06F11/00 主分类号 G01R31/3185
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