| 摘要 |
PROBLEM TO BE SOLVED: To allow the circuit to accurately grasp a switch timing through the addition of a simple circuit with respect to the phase locked loop circuit whose loop filter constant is changed between an initial frequency lock state and a steady-state. SOLUTION: A phase difference signal resulting from comparison between an input signal 101 and an output of a voltage controlled oscillator 109 is multiplied with constants α0, β0 at multipliers 104, 105 respectively in the initial frequency lock state. Outputs of an integration device 106 and the multiplier 105 are added and smoothed to make an output of the voltage controlled oscillator 109 close to the input signal 101. A sample-and-hold circuit 112, a storage element 113, a subtractor 114 and an absolute value circuit 115 are used to obtain a change in the integration signal 107 per unit time. When the change is smaller than a prescribed value γ, it is discriminated that the state is a steady-state and new constants α1, β1 are used. |
