发明名称 BINARY DATA COMPRESSION AND EXPANSION CIRCUIT, BINARY DATA TRANSFER SYSTEM USING SAME, AND BINARY DATA COMPRESSION AND EXPANSION METHOD
摘要 <p>PROBLEM TO BE SOLVED: To allow a method to have provision for high rate transfer without the need for a basic clock at a high frequency even when data compression or expansion is applied to binary data whose transfer rate is high. SOLUTION: A discrimination circuit 132 discriminates whether binary image data in x-bit are all '0s' (all '1s') data or mixed data of '0s' and '1s'. In the case of the mixed data, an output circuit 136 adds header information denoting a fact of mixed data to the binary image data in x-bit and outputs the resulting data to a transmission line 30. In the case of all '0's' (all '1s') data, a detection circuit 134 detects how many numbers of the all '0s' (all '1s') data being the binary image data in x-bit are consecutive. The output circuit 136 adds header information denoting a fact of all '0s' (all '1s') data to the binary image data in x-bit representing the detection result and outputs the resulting data to the transmission line 30.</p>
申请公布号 JPH09252256(A) 申请公布日期 1997.09.22
申请号 JP19960087255 申请日期 1996.03.14
申请人 DAINIPPON SCREEN MFG CO LTD 发明人 MITSUKI KIYOOMI
分类号 H04N19/70;H03M7/30;H03M7/46;H04N1/413;H04N7/24;H04N19/00;H04N19/85;H04N19/93;(IPC1-7):H03M7/30 主分类号 H04N19/70
代理机构 代理人
主权项
地址