| 摘要 |
PROBLEM TO BE SOLVED: To reduce the using memory capacity used for a test pattern generator by shortening the processing time of generating the pattern. SOLUTION: A GL fault list 105 and RTL fault list 112 are input by a difference extractor 113, the difference is extracted to form a differential fault list 114, a test pattern is generated by a GL test pattern generator 106 based on the list 114, and a test pattern is generated by an RTL test pattern generator 115 based on the list 112. These patterns are used as test patterns used to detect the fault of the logic circuit. Thus, the process of the generator 106 is reduced. |
