| 摘要 |
The system provides a smoothing arrangement for a clock signal, or a reduction in its irregularity. The system comprises a buffer memory (1), of an FIFO type, receiving the data (De) at the repetition rate of the clock (H) to be smoothed. The buffer memory then restores the data (Ds) at the repetition rate of the smoothed clock (Hs). The smoothed clock signal has a frequency equal to the average value of the initial clock signal, which experiences variations. A 'memory half full' signal (Shf) is integrated digitally into a binary word (Ni). An oscillator with a digital control (3) adds and accumulates (31) the associations of this word (Ni) with a preposition word (Np) at the repetition rate of a reference clock signal (Href). The most strongly weighted bit is extracted to form the output clock signal, which has been smoothed. |
