发明名称 DECODING CIRCUIT FOR MULTIPLEX VIDEO SIGNAL
摘要 <p>PROBLEM TO BE SOLVED: To allow a newly selected program to be quickly displayed on a display screen by selecting a connection state between a reception means and any of buffer circuits and a connection state between a decoding means and any of the buffer circuits. SOLUTION: A tuner 2 provides an output of an MPEG bit stream of a selected channel, a PID decoder 3 decodes a PID and the decoded stream is fed to a control circuit 11. Plural output terminals of an input selection circuit 4 connect respectively to a single decode buffer 5 and plural intra buffers 6-8 and output terminals of the buffers 5-8 connect to plural input terminals of an output selection circuit 9 respectively. Then a decode output obtained from an MPEG decoder 10 connecting to an output terminal of the output selection circuit 9 is fed to a TV receiver, on which an image is displayed. In this case, the selection of any buffer by the input selection circuit 4 and the output selection circuit 9 is controlled respectively by switching signals S1, S2 fed from the selection operation control circuit 11 depending on a program.</p>
申请公布号 JPH09247686(A) 申请公布日期 1997.09.19
申请号 JP19960054295 申请日期 1996.03.12
申请人 SANYO ELECTRIC CO LTD 发明人 SUNAKAWA OSAMI
分类号 H04N19/50;G06T9/00;H04N5/44;H04N7/00;H04N7/08;H04N7/081;H04N19/102;H04N19/159;H04N19/162;H04N19/423;H04N19/44;H04N19/503;H04N19/593;H04N19/70;(IPC1-7):H04N7/32 主分类号 H04N19/50
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