发明名称 CELL PROCESSING SYSTEM FOR ATM CHANNEL INTERFACE
摘要 <p>PROBLEM TO BE SOLVED: To obtain the system with high maintenance performance through an efficient configuration with a smaller size and offering simple test and inspection by providing plural cell processing sections each having a single cell processing function throughout a channel. SOLUTION: A signal inserted from a subscriber channel is converted into a desired electric signal by a physical termination section 60 and given to a frame termination section 61, in which frame synchronization and section overhead processing and pass overhead processing are conducted. Furthermore, a cell processing section 62 conducts header synchronization and cell assembling the signal is converted into a cell format and physical layer processing is terminated. An alarm cell extract/monitor section 63 inserts an alarm cell and sets a Y bit flag. Thus, cells are processed as if they were passed through an MC extract/monitor section 64, an OAM cell processing section 67, a UPC section 13, a charging processing section 14 and an MC insert section 68 and inserted by an alarm cell insert section 69.</p>
申请公布号 JPH09247184(A) 申请公布日期 1997.09.19
申请号 JP19960055765 申请日期 1996.03.13
申请人 FUJITSU LTD;NIPPON TELEGR & TELEPH CORP <NTT>;OKI ELECTRIC IND CO LTD;NEC CORP;HITACHI LTD 发明人 KAWARAI KENICHI;NAGATO YUJI;YAMANAKA NAOAKI;YOSHII NOBUYUKI;SUZUKI KOJI;OKAMOTO MANABU
分类号 H04Q3/00;H04L12/28;H04L12/70;H04L12/931;H04L12/951;(IPC1-7):H04L12/28 主分类号 H04Q3/00
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