发明名称 PLL FREQUENCY SYNTHESIZER
摘要 PROBLEM TO BE SOLVED: To switch a frequency without affecting the characteristics of a PLL itself by electric change in switching the frequency by controlling the loop gain of a digital filter by control information from the outside. SOLUTION: The digital filter 6 is adopted as a loop filter. Then, a cut-off frequency is specified by the control information from an external control terminal 11. Thus, the band and gain of a loop are arbitrarily changed even though it is physically single constitution. As a result, since no plural loop filters are physically required, the probability that frequency lock is released by noise or the like is lowered.
申请公布号 JPH09246965(A) 申请公布日期 1997.09.19
申请号 JP19960057309 申请日期 1996.03.14
申请人 NEC CORP 发明人 ISHII KATSUHIRO
分类号 H03L7/18;H03L7/089;H03L7/093;H03L7/095;H03L7/107;H03L7/183;(IPC1-7):H03L7/18 主分类号 H03L7/18
代理机构 代理人
主权项
地址