发明名称 Computer implementation of security mode within processor
摘要 The method involves executing instructions provided by a source external to a processor. The instructions is supplied to the processor via I/O to the processor, and, upon receiving an interrupt specifying a secure function, the following sub-steps are performed. The I/O to the processor is disabled, while the secure function specified by the interrupt is performed. The instructions for the secure function are stored in a read-only memory within the processor. On completion of performing the secure function, it then requires executing an exit routine, which enables I/O to the processor by a hardware control circuit and allows resumption of execution of instructions provided by the source external to the processor. The instructions for the exit routine are stored within the read-only memory.
申请公布号 FR2746199(A1) 申请公布日期 1997.09.19
申请号 FR19960003303 申请日期 1996.03.15
申请人 VLSI TECHNOLOGY INC 发明人 TAKAHASHI RICHARD J
分类号 G06F12/14;(IPC1-7):G06F9/06 主分类号 G06F12/14
代理机构 代理人
主权项
地址