发明名称 METHOD AND DEVICE FOR THREE DIMENTIONAL FORM SIMULATION
摘要 PROBLEM TO BE SOLVED: To conduct three dimentional form simulation on a semiconductor device in a short period of time by sharply reducing the memory capacity required for the simulation. SOLUTION: A margin region, where prescribed margin length is added, is provided on the boundary part of an input mask pattern split part and a mask pattern data and on the circumference of a mask pattern, the above- mentioned region is plotted three-dimensionally, other region is brought in the state of two dimensional data, and they are housed in a data housing part 3b. The two dimensional data is treated by a two dimensional configuration simulation treatment part 3c as two dimensional configuration, the three dimensional data is treated by a three dimensional configuration simulation treatment part 3d as a three dimensional configuration, the two dimensional configuration is treated into the three dimensional configuration, it is combined with the three dimensional configuration, which is brought into the state of three dimensional data, by the three dimensional configuration simulation treatment part 3d, and a configuration plotted three-dimensionally is indicated on an indication device 4.
申请公布号 JPH09246345(A) 申请公布日期 1997.09.19
申请号 JP19960049766 申请日期 1996.03.07
申请人 HITACHI LTD 发明人 NAKAMURA TAKAHIDE;SATO HISAKO;TSUNENO KATSUMI;KUNITOMO HISAAKI;AOYAMA JINKO;MASUDA HIROO
分类号 H01L21/66;G06F17/00;G06F17/50;G06F19/00;G06Q50/00;G06Q50/04;H01L21/00;H01L21/02 主分类号 H01L21/66
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