| 摘要 |
PROBLEM TO BE SOLVED: To increase delay performance and the throughput of product sum operation by outputting an addition sum as a product sum operation result and also outputting even a carry-out output which exceeds specific bits. SOLUTION: A multiplication array 106 is a code extension type multiplication array part, generates and adds (M/2) partial products with a multiplicand and the output of a booth encoder 104, and compresses them into two internal products and outputs them. A carry storage adder 107 adds the two intermediate products outputted from the multiplication array 106 to cumulative data and narrows down outputs to two outputs. A two-input adder 108 is an (M+N)-bit final carry propagation adder which adds the two outputs from the carry storage adder 107, outputs the addition sum as the product sum operation result, and also outputs the carry-out output which exceeds (M+N) bits. Then an exclusive OR gate 109 exclusively ORs the output from an overflow predicting circuit 105 and the carry-out output of the two-input adder 108 and outputs the exclusive-OR output as an overflow. |
