| 摘要 |
<p>PROBLEM TO BE SOLVED: To enable the speculative execution of a load instruction by predicting the load address of the load instruction by a parallel high-speed data processor such as a pipeline processor. SOLUTION: A load address cache 101 stores a tag as a specific bit part of the PC value of the load instruction, a last load address, a last difference value as the difference value of the load address, and a state bit S by a specific number of groups. A comparator 102 detects a tag matching the specific bit part of the PC value of a fetched load instruction. An adder 103 reads a last load address Ar and a last difference valueΔr corresponding to the tag whose coincidence is detected by the comparator 102 out of the load cache 101, adds them, and outputs the result as a predicted address Ap. A control part 104 makes a predictive decision and updates the contents of the load address cache 101 once a correct address becomes clear by performing address calculation corresponding to the load instruction at an execution stage.</p> |
